1. Field of the Invention
The present invention relates to switching power conversions, and more particularly to switching power conversions with adjustable minimum on-time.
2. Description of the Related Art
In supplying the power for electronic equipments, switching power converters are widely adopted due to the advantages of high conversion efficiency and small component size they possess.
FIG. 1 shows the architecture of a typical AC-to-DC power adapter. As shown in FIG. 1, the architecture realizing a fly-back type AC-to-DC power converter, at least includes: a PWM controller 100, an input rectifier and filter 101, a main transformer 102, an output rectifier and filter 103, a feedback network 104, an NMOS transistor 105, a flux releasing circuit 106 and a resistor 107.
In the architecture, the PWM controller 100 is used for generating a PWM signal Vout with a duty cycle in response to both a current sensing voltage VS and a reference voltage (not shown in FIG. 1) which is a function of a feedback signal VFB. When the current sensing voltage VS exceeds the reference voltage, a reset signal (not shown in FIG. 1) is generated to pull down the PWM signal Vout to end the duty cycle.
The input rectifier and filter 101 is used for generating a first DC voltage according to an AC input power source.
The main transformer 102 and the output rectifier and filter 103 are used to transfer the first DC voltage to a DC output voltage VO.
The feedback network 104 is used to generate the feedback signal VFB according to the DC output voltage VO.
The NMOS transistor 105 is used to control the power transformation through the main transformer 102 in response to the PWM signal Vout.
The flux releasing circuit 106 comprising a diode 108 is coupled with the primary side of the main transformer 102 for releasing the magnetic flux to protect the NMOS transistor 105 when the NMOS transistor 105 is off.
The resistor 107 is used for carrying a drain current IP of an NMOS transistor to exhibit the current sensing voltage VS.
Through a periodic on-and-off switching of the NMOS transistor 105, which is driven by the PWM signal Vout generated from the PWM controller 100, the input power is transformed through the main transformer 102 to the output.
However, when the PWM signal Vout makes a low-to-high transition, the diode 108 will stay on for a while due to a reverse recovery time of the diode 108, and there will be a reverse recovery current flowing down through the flux releasing circuit 106 to shift up the current sensing voltage VS across the resistor 107. If the current sensing voltage VS is shifted up to a level greater than the reference voltage, the reset signal will make a low-to-high transition and a reset glitch is generated. As a result, the duty cycle will be ended at a wrong time and will fail the power conversion.
One solution that conventional power converters utilize to solve this problem is to mask the reset signal with a leading edge blanking (LEB) signal so that during a blanking period the duty cycle will not be ended.
Please refer to FIG. 2, which shows a prior art circuit diagram for eliminating a reset glitch of a switching power converter. As shown in FIG. 2, the prior art circuit includes a comparator 201 and a Logic-AND gate 202. The comparator 201 is used to generate a reset signal according to a reference voltage Vref and a current sensing voltage VS. The Logic-AND gate 202 is used to generate a controller reset signal according to the reset signal and a conventional LEB signal.
To effectively mask the possible glitches in the reset signal, the conventional LEB signal is designed to have a blanking period covering the whole period of the reverse recovery time. Please refer to FIG. 3, which shows the waveform diagram according to the prior art circuit in FIG. 2, illustrating the process of eliminating a reset glitch. As shown in FIG. 3, a blanking period Tblank is predetermined for eliminating all possible reset glitches during a reverse recovery time TRR.
Although the design of the blanking period Tblank may be able to eliminate all possible reset glitches during the reverse recovery time TRR, it also sets a minimum limit to the turn-on time of the NMOS transistor 105 in FIG. 1. If the required period of a duty cycle is shorter than the blanking period Tblank, the duration of the duty cycle is not going to take the required period but take the blanking period Tblank in stead. In this case, there will be over-power supplying to a load of the switching power converter in the successive duty cycles. As the over-power being accumulated in the form of an increasing magnetic flux during the successive duty cycles, the load of the power converter will be crashed by an over rating current from the increasing magnetic flux.
Therefore, there is a need for providing a solution capable of preventing over supplying power to the load of a switching power converter in the prior art circuit.
Seeing this bottleneck, the present invention proposes a novel topology for generating a PWM signal capable of adaptively providing a blanking period of the duty cycles to prevent over supplying power to the load.